Power Semiconductor Parameter Glossary
Twenty-four terms that decide whether a device is specified correctly. Each entry gives the definition first, then the practical consequence that the definition implies — and the conditions under which the number means nothing.
Most component disputes trace back to a parameter compared without its conditions — an RDS(on) at 25 °C against one at 125 °C, a Trr quoted without a temperature, a "175 °C rated" device run at 175 °C. These definitions are written to remove that ambiguity: each one states what the number means and what it does not mean.
A
- Avalanche energy (EAS) and avalanche current (IAR)
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The single-pulse energy and current a device can absorb in avalanche breakdown without damage, quoted with a test inductance and starting junction temperature.
Avalanche rating is a ruggedness statement for a single event, such as an unclamped inductive load at turn-off. It is not a licence for repetitive avalanche: the energy per event must be small compared with EAS and the repetition rate low enough for the junction to cool, otherwise the failure is thermal and happens months later.
B
- BVDSS — drain-source breakdown voltage
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The maximum drain-source voltage the device blocks with the gate at zero, measured at a specified leakage current such as 250 µA.
Breakdown voltage falls slightly with temperature but rises sharply at low temperature, so a 650 V device is genuinely 650 V at −40 °C. The practical margin question is not BVDSS but the peak drain voltage in your circuit, which includes leakage-inductance ringing — a 650 V part in a 375 V bus with a poor clamp can see 700 V.
- Body diode
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The intrinsic p-n junction between drain and source in a MOSFET, which conducts in the reverse direction and has its own forward drop and recovery behaviour.
The body diode is why a synchronous rectifier conducts during dead time — and why the dead time must be short. Its reverse recovery is fast in a modern trench device but not zero, and in a SiC MOSFET the body diode forward drop is high enough (around 4–5 V) that continuous conduction through it will destroy the device thermally even though the current is within rating.
C
- Coss and Eoss — output capacitance and stored energy
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Coss is the drain-source capacitance with the gate off; Eoss is the energy stored in it, which is dissipated each switching cycle in a hard-switched topology.
Coss falls steeply as drain voltage rises, so the small-signal value at 25 V is not the value that governs loss at 400 V. Eoss, not Coss, is the loss-relevant figure. In a super junction device Coss is highly non-linear, and the energy returned during soft switching is only part of what was stored — a detail that surprises designers moving from planar parts.
- C-SAM — acoustic scanning microscopy
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An imaging method using ultrasound to detect delamination and voids inside a package without opening it.
C-SAM is the standard tool for finding delamination between mould compound and die, which is the usual precursor to a humidity failure. X-ray shows dense material and voids in solder; ultrasound shows interfaces that are no longer bonded. A supplier with both can answer "why did this unit fail" rather than "the sample passed".
D
- Derating
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Operating a device below its rated voltage, current or temperature to obtain a defined lifetime and failure rate in the application.
A common industrial rule is to keep junction temperature at or below 125 °C even when the device is rated 150 °C, and to keep peak voltage below 80% of BVDSS. Taken literally, that halves the 25 °C current rating of a TO-220F part in a 55 °C rack. Derating is a design decision that must be written down, because the same part quoted at its headline rating tells you nothing about life expectancy.
- Die attach
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The process of bonding a semiconductor die to its lead frame or substrate, providing both mechanical fixing and the primary thermal path.
Die attach voiding is one of the most consequential and least visible defects in packaging: a 10% void area can raise thermal resistance enough to halve the current a part can carry. It is controlled by X-ray sampling against an internal void limit, and by C-SAM when delamination is suspected.
F
- Figure of merit (FOM)
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A single number combining two competing parameters — most commonly RDS(on) × Qg — used to rank MOSFETs for a switching application.
FOM is only meaningful within one voltage class and one application frequency. A device with a better RDS(on) × Qg figure can still lose in a 20 kHz hard-switched design where conduction dominates, and win at 200 kHz where drive loss dominates. Treat FOM as a shortlist tool, then calculate loss at your actual conditions.
G
- GPP — glass passivated pellet
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A diode die whose junction is protected by a glass passivation layer, giving stable blocking behaviour under humidity and temperature stress.
GPP construction is the default for bridge rectifiers and fast recovery diodes above a few hundred volts, because the glass layer seals the junction edge against ionic contamination. A non-passivated or polymer-passivated die is cheaper and noticeably less stable in humid environments — a distinction rarely visible in a quotation.
H
- HTRB — high-temperature reverse bias
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A reliability test applying rated reverse voltage at elevated temperature for a defined duration, with electrical measurements at read points.
HTRB stresses the junction termination and passivation, where mobile ions and surface charge cause breakdown walkout. It is the standard screen for blocking stability, but it says nothing about humidity or mechanical stress. A report quoting "passed HTRB" without duration, temperature and sample size is not evidence of anything.
- H3TRB — high-humidity high-temperature reverse bias
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A reliability test applying reverse bias at elevated temperature and high relative humidity, typically 85 °C and 85% RH.
H3TRB is the test that predicts field failures in humid, non-airconditioned enclosures — telecom cabinets, outdoor lighting, solar inverters. Moisture plus bias drives corrosion and ionic migration at the passivation edge. For equipment with a ten-year life in a humid climate, H3TRB data matters more than HTRB, and many suppliers quote only the latter.
I
- IFSM — non-repetitive surge current
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The peak forward current a diode can withstand for a single half-sine pulse of stated duration, usually 8.3 or 10 ms, from a stated starting junction temperature.
IFSM is a non-repetitive rating. In a capacitive-input bridge, inrush repeats every time the product is switched on, and repeated surge is a thermal problem rather than a surge-rating problem. Sizing a bridge on IFSM alone is how a 2 A bridge ends up in a 1 A load and still fails in the field.
K
- Kelvin source connection
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A separate source return from the die to the gate driver, so that gate current does not flow through the power source inductance.
Without a Kelvin connection, the di/dt in the source inductance adds to the gate voltage and slows or re-triggers the device. At silicon switching speeds this is a refinement; with SiC switching in 20 ns, it is the difference between a working design and one that fails at turn-off. Packages such as TO-247 4-pin and TOLL4 exist to provide it.
P
- PDFN / TOLL — surface-mount power packages
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Leadless or clip-bonded surface-mount packages with a large exposed pad, used where a through-hole package will not fit or where source inductance must be minimised.
PDFN 5×6 and TOLL4 have far lower package inductance than TO-220, which matters more with SiC and with high-current synchronous rectifiers. They also move the thermal problem to the PCB: the exposed pad must have enough copper and thermal vias, and a 220 A device in PDFN on a two-layer board is a design error that no derating table will fix.
Q
- Qg — total gate charge
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The charge that must be delivered to the gate to drive the device from off to fully on at a stated drain voltage and current.
Qg sets gate-drive loss (Qg × VGS × frequency) and, more importantly, how fast the device can switch with a given driver current. Doubling switching frequency doubles drive loss with the same Qg — which is why SGT and super junction devices with low Qg exist, and why a 20 nC part at 200 kHz needs a driver that can source 4 A.
- Qrr and Trr — reverse recovery charge and time
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The charge and duration of reverse current that flows when a diode, having been conducting, is suddenly reverse-biased.
Qrr is the number that costs money in a hard-switched converter: it flows through the opposing switch at turn-on and adds a loss spike. Trr is meaningless without its test conditions — forward current, di/dt and starting junction temperature — and typically rises 50–80% from 25 °C to 125 °C. SiC Schottky diodes have no minority-carrier recovery, so their Qrr is effectively zero.
R
- RDS(on) — drain-source on-resistance
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The resistance between drain and source when the MOSFET is fully enhanced, quoted at a stated gate voltage, drain current and junction temperature.
RDS(on) rises with temperature — typically 40–70% from 25 °C to 125 °C for a silicon trench device. A 5.5 mΩ part is therefore nearer 8 mΩ when hot, and a conduction-loss calculation done at 25 °C underestimates heat by about 45%. Always read the temperature at which the value was taken before comparing two parts.
- RθJC — junction-to-case thermal resistance
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The steady-state temperature rise per watt dissipated, measured from the semiconductor junction to the package case.
RθJC is the only part of the thermal path the package supplier controls; the heatsink, the interface material and the ambient belong to the system. For a TO-220F at 2 W and RθJC near 2 °C/W, the case sits 4 °C above ambient-plus-heatsink rise — small compared with the 40 °C a modest heatsink adds. Which is why "the package is rated 175 °C" rarely decides a design.
S
- Super junction (charge-compensated) MOSFET
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A high voltage MOSFET structure using alternating p and n columns in the drift region so that the drift layer can be heavily doped while still blocking high voltage.
The result is a large reduction in RDS(on) per unit area at 600–650 V — typically 3 to 5 times better than a planar part of the same die size. The trade-off is a highly non-linear Coss and a sharper switching edge, both of which make EMI and low-load efficiency worse. Super junction is not universally better; it is better where conduction loss dominates.
- SGT — shielded gate trench MOSFET
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A trench MOSFET with a source-connected shield electrode beneath the gate, which reduces gate-drain capacitance and gate charge.
SGT devices dominate 30–100 V synchronous rectification because lower Qg at the same RDS(on) cuts drive loss and switch-node ringing. In a 48 V to 12 V converter running at 300 kHz, the difference between a plain trench and an SGT part can be a full efficiency point.
T
- TCT — temperature cycling test
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Repeated cycling between two chamber temperatures to stress the mismatch in thermal expansion between die, attach, bond wire and mould compound.
Failures from temperature cycling appear as solder-attach cracking and wire-bond lift-off, both of which are latent: the device passes final test and fails after a few hundred cycles in the field. Cycle count and dwell time must be stated, because 500 cycles from −40 to 125 °C is a different test from 1000 cycles from 0 to 100 °C.
- TO-220F vs TO-220 — isolated versus exposed tab
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TO-220F is the fully isolated full-pack version of TO-220, with mould compound covering the metal tab; TO-220 exposes the tab for direct heatsink contact.
TO-220F removes the need for an insulating pad and its thermal penalty, at the cost of a higher junction-to-case thermal resistance. In an offline power supply it is usually the right choice because isolation is mandatory anyway. Choosing TO-220 with a mica pad to save a few cents per unit often costs more in assembly labour than it saves.
V
- VGS(th) — gate threshold voltage
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The gate-source voltage at which a specified small drain current begins to flow, marking the onset of conduction rather than full enhancement.
VGS(th) is not the voltage at which the device is fully on. A part with VGS(th) of 1.2 V may need 4.5 V or 10 V to reach its rated RDS(on), and driving it at 3.3 V from a microcontroller pin puts it in the linear region where it dissipates far more than the datasheet implies. Check the RDS(on) test condition, not the threshold.
W
- Wire bonding
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The process of connecting die pads to package leads with fine wire, typically copper or gold, using thermosonic or ultrasonic bonding.
Copper wire carries more current than gold at the same diameter but is harder and needs more careful parameter control to avoid cratering the die. Bond integrity is verified by wire pull and die shear against JESD22 limits, measured per shift rather than per order — bond strength drifts with tool wear, not with the drawing.
Definitions follow JEDEC JESD22 and JESD24 terminology where those standards apply. Where industry usage differs from the standard, the practical usage is noted in the detail paragraph — because the datasheet you are reading usually follows the industry habit, not the standard.
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