Super Junction vs Planar MOSFET
Super junction MOSFETs cut on-resistance by 3–5×, but their non-linear Coss and sharp edge change EMI, light-load efficiency and avalanche behaviour.
OCENME Engineering · Published November 11, 2026 · 4 min read
Super junction MOSFETs achieve 3–5 times lower RDS(on) per die area than planar devices at 600–650 V, by charge compensation in the drift region. That advantage is real above roughly 150 W output, but it comes with a strongly non-linear Coss, a sharper switching edge and lower avalanche capability, which cost EMI margin and low-load efficiency.
Key points
- Charge compensation lets the drift region be doped 10× higher, which is where the RDS(on) gain comes from
- Coss is highly non-linear, so Eoss at 400 V is not what the small-signal value suggests
- Sharper dv/dt means more EMI, and a snubber or a slower gate resistor eats part of the efficiency gain
- Planar parts still win on avalanche robustness, cost and EMI-marginal designs
What “charge compensation” actually changes
A planar high voltage MOSFET blocks voltage with a thick, lightly doped drift layer. That layer’s resistance is the price of the voltage rating: to block 650 V, the silicon must be thick and lightly doped, and RDS(on) per unit area is set by physics.
A super junction structure replaces that uniform layer with alternating p and n columns. When the device blocks, the columns deplete into each other laterally, so the vertical doping can be roughly ten times higher while still supporting the same voltage. Higher doping, much lower resistance — a 3 to 5 times improvement in RDS(on) per unit area at 600–650 V.
The manufacturing difficulty is that the columns must be balanced. Any imbalance shifts the breakdown voltage and the avalanche behaviour. This is why super junction processes took years to mature and why the technology is concentrated in a small number of fabs.
The three costs of the gain
1. Coss becomes strongly non-linear
In a planar device, Coss falls smoothly as drain voltage rises. In a super junction device, the capacitance is high at low voltage and collapses as the columns deplete. Two consequences:
- The small-signal Coss value at 25 V overstates what happens at 400 V, so loss estimates done from the capacitance table are wrong in both directions.
- Stored energy Eoss is not simply ½CV², because C depends on V. Use the integrated Eoss curve.
2. The switching edge gets sharper
Lower Qg and lower Coss mean faster transitions. That is the point — but the same edge drives EMI. In a 65 kHz flyback, moving from planar to super junction typically gains 0.5–1.5 efficiency points and costs 3–6 dB of conducted margin at 30–100 MHz. If your design was passing with 2 dB to spare, it will now fail, and the filter you add to fix it consumes part of the gain.
3. Avalanche capability drops
The charge-compensated structure has less silicon volume to absorb avalanche energy and a smaller safe operating area. Datasheets still publish EAS, but the margin against repetitive events is thinner. In topologies with regular unclamped inductance — some welding and motor drive circuits — a planar part remains the more robust choice.
A worked comparison
Take a 200 W, 65 kHz flyback at universal input, 650 V class, 90% target efficiency.
| Item | Planar 0.45 Ω | Super junction 0.19 Ω |
|---|---|---|
| Conduction loss at 1.2 A RMS, 125 °C | 0.8 W | 0.35 W |
| Switching loss at 65 kHz, estimated | 0.9 W | 1.1 W (faster, but higher di/dt loss in clamp) |
| Drive loss | 0.05 W | 0.03 W |
| Net device loss | ~1.75 W | ~1.48 W |
| Efficiency effect at 200 W | baseline | +0.14% |
| EMI margin change | baseline | −3 to −5 dB |
The efficiency gain is real but small at 65 kHz, and the EMI cost is not. At 130 kHz the super junction part pulls ahead clearly: switching loss dominates and the lower Qg matters more than the sharper edge. This is why super junction became standard in adapters once quasi-resonant controllers pushed frequency up.
Where each actually belongs
Super junction is right when: output is above roughly 150 W, frequency is 65 kHz or higher, the design is efficiency-driven (DoE Level VI, CoC Tier 2, 80 PLUS), and there is board space for a proper snubber and filter.
Planar is right when: the design is cost-driven at low power, avalanche or surge robustness matters, the layout is compact and EMI-marginal, or the switching frequency is low enough that Qg is irrelevant.
SiC is right when: frequency exceeds roughly 100 kHz at 650 V, or the application wants the super junction benefit without the Coss non-linearity — at a price premium that only makes sense above a few hundred watts.
One more practical note: neither technology tolerates a bad layout. A super junction part with 40 nH of drain loop inductance will produce a turn-off spike that exceeds its rating at full load, and the failure will look like a device quality problem. Fix the loop before changing the part.
We list avalanche-rated planar types and super junction types with their own datasheets on the high voltage MOSFET page, and the glossary entry for Coss and Eoss explains why the integrated energy matters more than the capacitance value.
This article describes general manufacturing practice for machined and fabricated components. It is not a substitute for a drawing-specific engineering review — tolerances, material selection and process capability depend on the individual part.